1. Technical Field
This invention relates to a CAD system for designing a printed wiring board, a printed wiring board design method, a printed wiring board design device, and a method and device for an EMC design, applicable to the CAD system.
2. Description of Related Art
Electronic equipment in recent years has advanced the progress of downsizing, high functionality and digitalization, which has entailed an increase in unnecessary radiation noise exerting an influence on other electronic equipment of an electromagnetic wave radiated by the electronic equipment of interest, which has increasingly enhanced more and more the necessity for a measure to diminish the unnecessary radiation noise. Whereas, since there is a relationship of a trade-off between the measures to be taken and downsizing, EMC design has become technically more and more difficult to cope with every year.
Various noise reduction designs have been studied such as high frequency isolation of IC power supply wiring using an inductance element and a capacitance element on a digital circuit board, which is a source of generation of unnecessary radiation noise and a strip structure of signal wiring.
Especially, since a bypass capacitor inserted between the power supply terminal and the GND terminal of a digital IC not only stabilizes a high frequency variation in a power supply voltage generated in company with a switching operation of the IC by supplementing the variation with an accumulated charge, but also feeds back a high frequency component to the GND terminal of the IC to thereby play a role in confirming high frequency noise in the neighborhood of the IC, the inserted bypass capacitance has been widely known as the most basic and important means in the unnecessary radiation noise reduction for a circuit board, which leads to proposals offered on a printed wiring board design device using many of the schemes and tools concerning placement of a bypass capacitor and wiring.
For example, a proposal on an automatic placement, wiring devices offered in Patent document 1 (JP 05-205011) in which a board is divided into plural wiring regions and not only are densities of existing components and wires leveled over the regions, being made balanced therebetween, but the shortest wiring length is also achieved, and besides, another proposal on an automatic placement scheme is offered in Patent document 2 (JP 2000-67089) in which a projection area of components and wires is minimized.
The design device, however, is extremely insufficient with respect to the unnecessary radiation noise reduction of a circuit board. The reason why is such that, in the actual board design, a necessity arises for considerations to be given to many of design items such as an operating frequency of an IC, a thickness of a wiring layer or a wire and a capacity characteristic of a capacitor in addition to a distance between the IC and the bypass capacitor and a wiring length for reduction of EMC in order to reduce EMC. Therefore, the work becomes indispensable that design data is deliberately examined based on a design rule obtained by organizing the items to be considered, which is difficult and extremely time consuming, having led to a problem of inability in implementing a sufficient EMC design in a limited design time.
There has been contrived a method as a measure for improvement on such a problem in which placement and wiring data for a bypass capacitor to be inputted to a CAD system used for a printed wiring board design is checked in real time, and if the data falls outside of the allowable range, a warning message is displayed on a screen so that a designer is urged to improve the design to thereby confine the CAD data within the allowable range defined by the design rule. For example, FIG. 11 is a descriptive diagram showing a design flow on CAD according to the conventional method, wherein a designer compares design data with which placement and wiring are temporarily conducted with a design rule DB and component characteristics DB to thereby perform a pass/fail determination and if the determination is fail, a warning message is displayed on a screen.
Patent document 1.JP-A No. 05-205011Patent document 2.JP-A No. 2000-67089Patent document 3.JP-A No. 2001-125943Patent document 4.JP-A No. 2002-16337